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7.0 JTAG INTERFACE
The easiest way to load an FPGA configuration (*.bit) file to the FPGA is to run the BitLoadApp
software then select and program a file from the local hard drive directly to the SPI Flash. Once
written to the SPI Flash, the configuration will load to the FPGA and execute. Alternatively, a
traditional JTAG header location is provided on the DLP-HS-FPGA giving the user access to the
specific pins required by the development tools. (Refer to the schematic contained within this
datasheet for details.)
8.0 EEPROM SETUP / MPROG
The DLP-HS-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively
to load an FPGA configuration (*.bit) file to the SPI Flash. This configuration data is automatically
transferred to the FPGA when power is applied to the module or when the PROG Pin is driven low
and then released by the application software. Channel B is used for communication between the
FPGA and host PC at run time. A 93LC56B EEPROM connected to the USB interface IC is used to
store the setup for the two channels. The parameters stored in the EEPROM include the Vendor ID
(VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX) and port
type (UART serial or FIFO parallel).
As mentioned above, Channel A is used exclusively for loading the FPGA’s configuration to the SPI
Flash, and Channel B is used for communication between the host PC and the DLP-HS-FPGA. As
such, the D2XX drivers and 245 FIFO mode must be selected in the EEPROM for Channel A.
Channel B must use the 245 FIFO mode, but it can use either the VCP or D2XX drivers. The VCP
drivers make the DLP-HS-FPGA appear as an RS232 port to the host application. The D2XX drivers
provide faster throughput, but require working with a *.lib or *.dll library in the host application.
The operational modes and other EEPROM selections are written to the EEPROM using the MPROG
utility. This utility and its manual are available for download from the bottom of the page at
www.dlpdesign.com .
Rev. 1.7 (May 2011)
7
? DLP Design, Inc.
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相关PDF资料
DLP-IOR4
MODULE LATCHING-RELAY 4-CH
DLP-TEMP-G
MODULE DATA-ACQUISITION 3-CH
DLP-TXRX-G
MODULE USB-TO-TTL SRL UART CONV
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DLP-USB245M-G
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相关代理商/技术参数
DLP-HS-FPGA3
功能描述:可编程逻辑 IC 开发工具 USB-to-FPGA Development Module
RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
DLP-HS-FPGA-A
功能描述:FPGA Embedded Module Spartan-3A, XC3S200A FT2232H 66MHz 32MB 制造商:dlp design inc. 系列:FPGA 零件状态:有效 模块/板类型:FPGA，USB ?? 核心处理器:Spartan-3A，XC3S200A 协处理器:FT2232H 速度:66MHz 闪存大小:- RAM 容量:32Mb 连接器类型:USB - B，引脚接头 大小/尺寸:3" x 1.2"（76.2mm x 30.5mm） 工作温度:0°C ~ 70°C 标准包装:1
DLP-IO14
功能描述:数据记录与采集 14-Channel Data-Acq Module
RoHS:否 制造商:Lantronix 描述/功能:Analog device server 显示器类型:None 电流额定值:
DLP-IO16
功能描述:界面模块 USB/Micro Dev Board
RoHS:否 制造商:4D Systems 产品:Serial Converters 通道/端口数量: 数据速率: 接口类型:USB, UART 工作电源电压:3.3 V, 5 V 最大工作温度:
DLP-IO20
功能描述:数据记录与采集 USB-BASED 20-CHANNEL DATA ACQUISITION MOD RoHS:否 制造商:Lantronix 描述/功能:Analog device server 显示器类型:None 电流额定值:
DLP-IO26
功能描述:开发板和工具包 - PIC / DSPIC USB/Micro Dev Board
RoHS:否 制造商:Microchip Technology 产品:Starter Kits 工具用于评估:chipKIT 核心:Uno32 接口类型: 工作电源电压:
DLP-IO8
功能描述:界面模块 USB-BASED 8-CHANL DATA ACQUSITION MODL
RoHS:否 制造商:4D Systems 产品:Serial Converters 通道/端口数量: 数据速率: 接口类型:USB, UART 工作电源电压:3.3 V, 5 V 最大工作温度:
DLP-IO8-G
功能描述:数据记录与采集 USB-BASED 8-CHANL DATA ACQUSITION MODL RoHS:否 制造商:Lantronix 描述/功能:Analog device server 显示器类型:None 电流额定值: